Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used as well, such as germanium, gallium arsenide or other materials described below. One type of wafer is a silicon-on-insulator (SOI) wafer. An SOI wafer includes a thin layer of silicon (an active layer) atop an insulating layer (i.e., an oxide layer) which is in turn disposed on a silicon substrate. A bonded SOI semiconductor wafer is a type of SOI structure.
Due to device width shrink, power conservation, super-high speed performance, and/or special applications in electronic industry, the demands on SOI (silicon on insulator) wafers are increasing. One challenge is to effectively remove the unbonded outer peripheral portion of an active layer wafer bonded to the support substrate in order to avoid delamination. Delamination can result in particle contamination in the process and/or device lines of the wafer.
When manufacturing an SOI wafer, outer peripheral portions of the two wafers to be bonded are subjected to R or T chamfering, or edge profiling (as further described below), in order to prevent wafer breakage, cracks and/or particle generation. Also, outer peripheral portions of a bonded substrate have uneven thickness due to wafering steps. Because of this uneven thickness, during the bonding process, the outer peripheral portion is either not bonded at all and/or weakly bonded. When an active wafer thickness is reduced with processes such as grinding, etching, polishing, etc., this unbonded portion is partially delaminated from the bonded substrate during the film thickness reducing processes. The delaminated parts cause problems for film thickness reduction, cleaning, and measurement processes. Furthermore, in device processes, the remaining unbonded portions are delaminated, which causes particle generation and severely impacts device yields.
There have been several prior art attempts to solve delamination. For example, FIGS. 1A-1D show a progression of steps for bonding a substrate wafer S and an active layer wafer A to each other and then chamfering the edge peripheral portion of the bonded wafer W. FIG. 1A shows the substrate below the active layer wafer, and FIG. 1B shows the bonded wafers. FIG. 1C shows a grinder G grinding the outer peripheral edges of the wafers, and FIG. 1D shows the complete SOI wafer W (note that the complete wafer is further processed). This method is believed to be substantively similar to that shown in Japanese Patent Application No. 1986-256621. Among other drawbacks of this example, the diameter of the wafer W is smaller than the standard wafer diameter, which causes problems for the downstream handling facilities and jigs.
In another prior art example shown in FIGS. 2A-2D, a bonded SOI wafer W is formed as described above from an active layer wafer A and a substrate wafer S. The wafer edges are ground as shown in FIGS. 2B-2C such that the entire outer edge of the active wafer A is ground off, but only a portion of substrate is ground off. This method is believed to be substantively similar to that shown in Japanese Patent Application No. 1989-227441. This method suffers from poor efficiency.
In the prior art example shown in FIG. 3A, the active wafer A is ground at its edges to form a ledge L (wafer A is thus a pre-ground wafer). The wafer A is bonded to substrate wafer S in FIG. 3B. In FIG. 3C, the top surface of the bonded SOI wafer W is ground to remove the ledge L, and the complete wafer is shown in FIG. 3D. The unbonded portion of the active layer wafer can thereafter be ground down. This method is believed to be substantively similar to that shown in Japanese Patent Application No. 1992-85827.
In prior art FIG. 4A, a bonded SOI wafer W is formed as described above from an active layer wafer A and a substrate wafer S. In FIG. 4B, the active wafer A is ground at its upper peripheral edge E to form the ledge L shown in FIG. 4C. To complete the wafer processing of FIG. 4D, selective etching, polishing and/or PAC (plasma assisted chemical etching) processes are used to remove the unbonded parts from the outer peripheral edge of the active layer wafer A. This method is believed to be substantively similar to that shown in U.S. Pat. No. 6,534,384 B2, which is incorporated herein by reference. As can be seen, many steps are required to form the complete wafer.
In prior art FIG. 5A, the active layer wafer A includes a groove R formed in its lower surface prior to bonding. The active wafer A is bonded to the substrate wafer S in FIG. 5B. This method is believed to be substantively similar to that shown in US Patent Application 2009/0203167 A1, which is incorporated herein by reference. In FIG. 5C, grinding is performed on wafer A on the opposite side from the groove R. The unbonded portion of the outer peripheral portion of the wafer A can be removed after grinding the wafer to predetermined thickness, as shown in the complete wafer W of FIG. 5D.
There remains an unfulfilled need for a wafer surface treatment method and a wafer that addresses the disadvantages of current methods of preventing delamination of the outer peripheral portion of an active layer of a bonded structure.